Benefit from our experience! FBE-ASIC GmbH offers all stages of digital ASIC design: Specification compilation (requirement engineering) Project management System engineering Implementation Verification Synthesis Introduction of test structures Timing analysis Pre-layout

A vital part of our design-flow is the specification compilation period. As the result of this period, an executable specification (highlevel RTL or SystemC) and a top level testbench will be generated. Thus, models of the design, possibly also including the target-processor (e.g. ARM, ARC) or a generic processor module, can be delivered to the customer at a very early stage, helping to speed up product generation (SW design) at the customer's site. Also, spec quality is improved since all functions of the later design can be checked before implementation, missing (or contradictory) requirements inside the specification are discovered at a very early stage. The top level testbench helps us to verify the design.

Of course, we may also provide FPGA based RapidPrototyping environments (see the FPGA page).

Benefit from the experience we gathered from several big ASIC projects in multimedia, telecom and instrumentation equipment !