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F-CSA104 - Quad CMOS Low-Noise Charge Sensitive Preamplifier

F-CSA104 contains 4 channels of charge sensitive preamplifiers with differential line drivers. It has particularly been designed for the use with semiconductor radiation detectors operating with liquid nitrogen as coolant (T = 77K/-196°C) .

F-CSA104 joins the formerly discrete input FET with the preamplifier in a single IC, thus forming the next step of integ­ration for better immunity to interference. F-CSA104's noise performance has been optimized for use with capacitive detectors of 0 - 100pF; flicker noise is reduced by use of a p-channel MOSFET as input transistor. In cases where noise matching to higher capacitance detectors is vital, an external p-channel FET may be connected to the IC.

A range of F-CSA104's parameters (including offset and preamplifier decay constant) can be programmed via an I2C interface. F-CSA104's linearity and offset have been designed for use with 14 bit ADC systems, thus being ideally suited for spectroscopy applications.

The high current drive differential line drivers allow for directly driving a 100 Ohm twisted pair cable.

F-CSA104 has been delivered from fab and is currently under evaluation (project in collaboration with Max-Planck-Institut für Kernphysik, Heidelberg).

F-CSA104
F-CSA104 Simplified block diagram

F-CSA104 Datasheet (pdf, 174kB)

Features

  • Very low noise (ENC=220e- @ Cdet = 30pF, T=27°, Tpeak = 20µs)
  • Temperature range -200°C ... +50°C
  • Fast differential outputs (trise < 30 ns)
  • Gain 5.84 mV/fC, 316 mV/MeV(Ge), 258mV/MeV(Si)
  • Input signal range ± 600 fC, ± 11MeV(Ge), ± 13MeV(Si)
  • 14 bit linearity for spectroscopy applications
  • Adjustable preamplifier time constant 1us ... 1.5ms
  • Optional connection of external p-channel FET
  • Optimized for detectors of 0 pF ... 100 pF
  • All stages DC coupled, triple offset suppression
  • I2C-interface for parameter adjustment

Electrical Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ENCRT


Input equivalent noise charge at room temper­ature

CR-(RC)4 shaper, peak time 20µs, AUTOSEL_N=1, RES_FDB_LO=0
Cdet = 0 pF
Cdet = 30 pF
Cdet = 100 pF







120
220
510





electrons
electrons
electrons

FWHM(Si)RT

“Electronic noise” contribution when used with silicon detector at room temperature

CR-(RC)4 shaper, peak time 20µs, AUTOSEL_N=1, RES_FDB_LO=0
Cdet = 0 pF
Cdet = 30 pF
Cdet = 100 pF





1.02
1.87
4.24





keV
keV
keV

ENCLT


Input equivalent noise charge at -200°C

CR-(RC)4 shaper, peak time 20µs, AUTOSEL_N=1, RES_FDB_LO=0, remaining settings “default -200°C”
Cdet = 0 pF
Cdet = 30 pF
Cdet = 100 pF






60
110
240






electrons
electrons
electrons

FWHM(Ge)LT

“Electronic noise” contribution when used with Germanium detector at -200°C

CR-(RC)4 shaper, peak time 20µs, AUTOSEL_N=1, RES_FDB_LO=0
Cdet = 0 pF
Cdet = 30 pF
Cdet = 100 pF





0.417
0.765
1.67





keV
keV
keV

gm,RT

Input transistor transconductance

Iinp=1mA (INP=h'08), T=27°C


19.7


mA/V

gm,LT

Input transistor transconductance

Iinp=1mA (INP=h'08), T=-200°C


39.2


mA/V

Cgate

Input capacitance

Input capacitance of input PMOS (W=9000µm, L=0.6µm)


7


pF

AV

Charge sensitivity
V(OUTP-OUTM) / Qin

AUTOSEL_N=1, RES_FDB_LO=0, remaining settings “default -200°C”,
Positive input charge Qin > 0


Negative input charge Qin < 0





5.84
315.7
258.1
5.84
315.7
258.1





mV/fC
mV/MeV(Ge)
mV/MeV(Si)
mV/fC
mV/MeV(Ge)
mV/MeV(Si)

Vpp

Dynamic range

AUTOSEL_N=1, RES_FDB_LO=0, remaining settings “default -200°C”,
Positive input charge Qin > 0


Positive input charge Qin > 0





600
11.1
13.6

600
11.1
13.6





fC
MeV(Ge)
MeV(Si)
fC
MeV(Ge)
MeV(Si)

INL

Integral nonlinearity

AUTOSEL_N=1, RES_FDB_LO=0, remaining settings “default -200°C”, measured after 1µs, LSB (14 bit) refered to dynamic range Vpp
Positive input charge Qin > 0
Negative input charge Qin < 0







2
1







LSB
LSB

XT

Interchannel crosstalk




1

Tr

Risetime 10%-90%

Qin = 40 fC
Qin = 541 fC (= 10 MeV(Ge) )


22
28


ns
ns

Ts

Settling time for 14 bit accuracy

Qin = 40 fC, ΔV(OUTP-OUTM)=14 µV
Qin = 541 fC, ΔV(OUTP-OUTM)=190 µV



560

530


700

700


ns

ns

T1/2

Preamplifier decay time (half life) for small Qin

Minimum value: RES_FDB_LO = 1,
FDB[5:1] = h'1F
maximum value: RES_FDB_LO = 0, FDB[5:1] = h'01



0.7




1530



µs

Ao,PA

Preamplifier open loop gain



120


dB

Ao,OP1

Line driver open loop gain



92


dB

ΔVin

Input voltage shift for max positive/negative signal after settling



0.44


µV

IDD

Current consumption

No traffic on I2C lines, no signal injected



60

mA

IDD,CH

Current consumption per channel (VSSA)

No signal injected



9.5

mA

Unless otherwise specified, all values given are for T=27°C,register settings „default 27°C“, VDDA=VDDD =-VSSA=-VSSS = 2.5V, GND=0V, Rload = 100 Ω; all values at -200°C have been derived from simulations with estimated models.

 
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