F-CSA104 - Quad CMOS Low-Noise Charge Sensitive Preamplifier
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F-CSA104 contains 4 channels of charge sensitive preamplifiers with differential line
drivers. It has particularly been designed for the use with
semiconductor radiation detectors operating with liquid nitrogen as coolant
(T = 77K/-196°C) .
F-CSA104 joins the
formerly discrete input FET with the preamplifier in a single IC,
thus forming the next step of integration for better immunity
to interference. F-CSA104's noise
performance has been optimized for use with capacitive detectors
of 0 - 100pF; flicker noise is reduced by use of a p-channel
MOSFET as input transistor. In cases where noise matching to
higher capacitance detectors is vital, an external p-channel FET
may be connected to the IC.
A range of F-CSA104's parameters (including
offset and preamplifier decay constant) can be programmed via an I2C
interface. F-CSA104's linearity and offset have been designed
for use with 14 bit ADC systems, thus being ideally suited for
spectroscopy applications.
The high current
drive differential line drivers allow for directly driving a 100
Ohm twisted pair cable.
F-CSA104 has been delivered from fab and is currently under evaluation
(project in collaboration with Max-Planck-Institut für Kernphysik, Heidelberg).
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F-CSA104 Simplified block diagram
F-CSA104 Datasheet (pdf, 174kB)
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Features
- Very low noise (ENC=220e- @ Cdet = 30pF, T=27°,
Tpeak = 20µs)
- Temperature
range -200°C ... +50°C
- Fast
differential outputs (trise < 30 ns)
- Gain
5.84 mV/fC, 316 mV/MeV(Ge),
258mV/MeV(Si)
- Input
signal range ± 600 fC, ±
11MeV(Ge), ± 13MeV(Si)
- 14
bit linearity for spectroscopy applications
- Adjustable
preamplifier time constant 1us ... 1.5ms
- Optional
connection of external p-channel FET
- Optimized for
detectors of 0 pF ... 100 pF
- All
stages DC coupled, triple offset suppression
- I2C-interface for
parameter adjustment
Electrical Characteristics
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Symbol
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Parameter
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Conditions
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Min
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Typ
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Max
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Unit
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ENCRT
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Input equivalent noise charge at
room temperature
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CR-(RC)4 shaper, peak
time 20µs, AUTOSEL_N=1, RES_FDB_LO=0 Cdet = 0
pF Cdet = 30 pF Cdet = 100 pF
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120 220 510
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electrons electrons electrons
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FWHM(Si)RT
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“Electronic noise”
contribution when used with silicon detector at room temperature
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CR-(RC)4 shaper, peak
time 20µs, AUTOSEL_N=1, RES_FDB_LO=0 Cdet = 0
pF Cdet = 30 pF Cdet = 100 pF
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1.02 1.87 4.24
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keV keV keV
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ENCLT
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Input equivalent noise charge at
-200°C
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CR-(RC)4 shaper, peak
time 20µs, AUTOSEL_N=1, RES_FDB_LO=0, remaining settings
“default -200°C” Cdet = 0 pF Cdet
= 30 pF Cdet = 100 pF
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60 110 240
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electrons electrons electrons
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FWHM(Ge)LT
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“Electronic noise”
contribution when used with Germanium detector at -200°C
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CR-(RC)4 shaper, peak
time 20µs, AUTOSEL_N=1, RES_FDB_LO=0 Cdet = 0
pF Cdet = 30 pF Cdet = 100 pF
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0.417 0.765 1.67
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keV keV keV
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gm,RT
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Input transistor transconductance
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Iinp=1mA (INP=h'08),
T=27°C
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19.7
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mA/V
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gm,LT
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Input transistor transconductance
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Iinp=1mA (INP=h'08),
T=-200°C
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39.2
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mA/V
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Cgate
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Input capacitance
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Input capacitance of input PMOS
(W=9000µm, L=0.6µm)
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7
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pF
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AV
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Charge sensitivity V(OUTP-OUTM) /
Qin
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AUTOSEL_N=1, RES_FDB_LO=0, remaining
settings “default -200°C”, Positive input
charge Qin > 0
Negative input charge Qin
< 0
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5.84 315.7 258.1 5.84 315.7 258.1
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mV/fC mV/MeV(Ge) mV/MeV(Si) mV/fC mV/MeV(Ge) mV/MeV(Si)
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Vpp
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Dynamic range
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AUTOSEL_N=1, RES_FDB_LO=0, remaining
settings “default -200°C”, Positive input
charge Qin > 0
Positive input charge Qin
> 0
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600 11.1 13.6 600 11.1 13.6
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fC MeV(Ge) MeV(Si) fC MeV(Ge) MeV(Si)
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INL
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Integral nonlinearity
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AUTOSEL_N=1, RES_FDB_LO=0, remaining
settings “default -200°C”, measured after 1µs,
LSB (14 bit) refered to dynamic range Vpp Positive
input charge Qin > 0 Negative input charge Qin
< 0
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2 1
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LSB LSB
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XT
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Interchannel crosstalk
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1
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‰
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Tr
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Risetime 10%-90%
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Qin = 40 fC Qin = 541
fC (= 10 MeV(Ge) )
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22 28
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ns ns
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Ts
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Settling time for 14 bit accuracy
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Qin = 40 fC, ΔV(OUTP-OUTM)=14
µV Qin = 541 fC, ΔV(OUTP-OUTM)=190
µV
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560
530
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700
700
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ns
ns
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T1/2
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Preamplifier decay time (half life)
for small Qin
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Minimum value: RES_FDB_LO =
1, FDB[5:1] = h'1F maximum value: RES_FDB_LO = 0, FDB[5:1] =
h'01
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0.7
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1530
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µs
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Ao,PA
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Preamplifier open loop gain
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120
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dB
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Ao,OP1
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Line driver open loop gain
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92
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dB
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ΔVin
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Input voltage shift for max
positive/negative signal after settling
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0.44
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µV
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IDD
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Current consumption
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No traffic on I2C lines, no signal
injected
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60
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mA
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IDD,CH
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Current consumption per channel
(VSSA)
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No signal injected
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9.5
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mA
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Unless otherwise
specified, all values given are for T=27°C,register settings
„default 27°C“, VDDA=VDDD =-VSSA=-VSSS = 2.5V,
GND=0V, Rload = 100 Ω;
all values at -200°C have been derived from
simulations with estimated models.
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