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System On Chip and Electronic System Level Design
Following Moore's law, IC complexity doubles every two years. The exponential growth, enabled by a stunning innovation speed in silicon process technology, has been fueled on the design side by the reuse of RTL-based IP. This IP reuse, however, has not yet been accompanied by a similar approach in architecture definition and verification. To keep pace with progress in technology development and to secure design quality, a new development process is needed, leaving RTL based system design and RTL simulation behind.
Despite according ESL methodologies being available for a number of years, the pain of poor or unclear system level performance seemingly has not been big enough. The time has come for the adoption of true ESL methods in combination with a new approach for SoC design, which is also reflected in latest EDA takeovers and standardization processes.
FBE-ASIC has been using SystemC for system level modelling and has been following the worldwide adoption of SPIRIT based SoC design methodologies and the usage of IP-XACT for years.
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