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last update : June 2017
Verification
RF Design
Mixed-signal
Digital Design
FPGA systems
SoC / ESL
Modelling
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Example SystemVerilog(OVM) / Mixed-signal
SystemVerilog OVM + Verilog-AMS class based environment for the verification of an industrial communication transceiver used for digital and mixed signal verification
two communication channels
master and slave mode
device configuration using SPI-TLM IF
API for test writers
scoreboard and coverage collection
verification management using Cadence-eManager
reference model contains complete internal memory structure to allow immediate checks
Examples:
Verilog
SystemVerilog(OVM)
Mixed-Signal
SystemC/SV based
SoC Automation
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